CoreSight is a hardware technology present in many modern ARM based Systems-on-Chips (SoC) which enables tracing of program execution and system events in a non-invasive way – without additional hardware or instrumentation of the analysed software and with negligible performance penalty. The objectives of the project were to evaluate CoreSight feature availability on a selection of SoCs, develop embedded software to interface with the CoreSight hardware on the selected platform and demonstrate the capabilities and performance of the developed solution using a representative use-case based on PROBA3 payload Application Software (ASW).
CoreSight feature availability was researched and reported. Embedded Trace Software Modules (ETSM) were developed for Xilinx Zynq Ultrascale+ ZCU104 board running Linux, interfacing with CoreSight via perf subsystem, supporting the required functionality and exposing it via PUS 6 and a custom PUS service over ethernet. The development of ETSM required modifications of the Linux kernel subsystems related to perf and CoreSight support. PUS C Deployment tool suite, developed by N7 Space, was used to design the PUS C services and generate the corresponding ASN.1 and ACN data type definitions, from which the telecommand/telemetry transcoders were automatically derived. Test and Tracing Support Modules (TTSM) were developed to interface an in-house software validation facility with ETSM. PROBA3 payload ASW was modified to remove its dependencies on PROBA3 hardware and to run on Linux via a thin RTEMS API emulation layer. The following capabilities were successfully demonstrated:
- trace download for post-mortem investigation,
Trace captured from an execution of non-instrumented code with artificially inserted bug. The trace lists the sequence of executed instructions which led to a crash, unlike a stack trace, which would show only the sequence of function calls.
- execution time profiling and verification,
Histogram of execution times of a block of code, captured without code instrumentation.
- as well as inter-core interference analysis.
Plot of bus access events (correlated with cache misses) with respect to code execution times, in various configurations of an interfering program running concurrently on a different processor core.
The developed solution has the potential to facilitate performance measurements, behaviour analysis, testing and debugging of on-board software, both on-ground and in-flight. The performance measurements may be a valuable input to software verification and various analyses (e.g. schedulability and inter-core interference).
Resources:
- PROBA3
- CoreSight
- Zynq Ultrascale+
- Zynq Ultrascale+ ZCU104
- RTEMS
- PUS C standard
- PUS C Deployment toolset
- ASN1SCC ASN.1/ACN compiler
- ASN.1
- ACN
Disclaimer: This work performed during this project was carried out under a programme of, and funded by, the European Space Agency. The views expressed here can in no way be taken to reflect the official opinion of the European Space Agency.